A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor

Abstract

Back-end-of-line (BEOL) compatible tungsten doped indium oxide (IWO) n-type channel transistor is proposed to achieve complementary logic operation with front-end-of-line (FEOL) p-type silicon transistor. To make the fully logic-voltage compatible, a novel stacked nanosheet structure of IWO transistor is designed to achieve high on-current density (Ion > 544 μA/μm) at VGS=1 V to compensate the relative low mobility in semiconducting oxide (~20 cm2/Vs). We demonstrate its performance using Technology Computer-Aided Design (TCAD). For design-technology co-optimization of IWO transistors, a customized monolithic 3D (M3D) process design kit (PDK) and related standard cell library using transistor-level partition are developed to investigate the trade-offs in power, performance, and area (PPA) in representative logic circuit designs such as Advanced encryption standard (AES), triple data encryption algorithm (DES3), and low-density parity-check (LDPC) circuits. The synthesis and simulation results show the M3D design could achieve an average of 35% area reduction under similar energy-delay-product (EDP).