Multilevel decomposition Discrete Wavelet Transform for hardware image compression architectures applications

K. K. Hasan, U. K. Ngah, M. Salleh
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引用次数: 8

Abstract

In this paper, flexible hardware architecture of multi-level decomposition Discrete Wavelet Transform (DWT) is proposed for image compression applications to eliminate redundant information from the transmitted images or video frames over the wireless channel. This architecture of DWT is described and synthesized with the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) based methodology. The design can be accommodated on any targeting Field Programmable Gate Array (FPGA) device with slight changes. It facilitates to images of size 64×64, 128×128, 256×256, and 512× 512 pixels and capable of seven levels of decomposition. In order to reduce computational complexities, Fast Haar Wavelet Transform (FHWT) is used. The reduction in the resource usage of this 2D DWT multilevel FPGA core can be used to counter severe hardware constraints of various wireless and mobile device applications.
多层分解离散小波变换在硬件图像压缩体系结构中的应用
为了消除无线信道中传输的图像或视频帧中的冗余信息,提出了一种灵活的多级分解离散小波变换(DWT)硬件结构。采用基于超高速集成电路(VHSIC)硬件描述语言(VHDL)的方法对DWT的结构进行了描述和综合。该设计可以适应任何目标现场可编程门阵列(FPGA)器件,只需稍加改动。它有助于处理尺寸为64×64, 128×128, 256×256和512x512像素的图像,并能够进行七层分解。为了降低计算复杂度,采用了快速哈尔小波变换(FHWT)。这种2D DWT多电平FPGA核心的资源使用减少可用于对抗各种无线和移动设备应用的严重硬件限制。
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