Output tracking control via TS-SCMAC and VDVs aPPROACH FOR tIME-dELAY sYSTEMS

Teng-Shung Chiang, Chian-Song Chiu, Peter Liu
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Abstract

This paper proposes an output tracking via TS-SCMAC and virtual desired variable (VDV) approach for a class of time-delay systems with uncertainties. The overall control output tracking system has H∞ control performance. The advantages of the proposed methodology are i) information of system equilibrium is not required simplifying the controller design. ii) overall output tracking system has H∞ control performances. Moreover, we consider the example of continuous stirred tank reactor system. The effectiveness of the proposed controller is validated by satisfactory numerical results.
基于TS-SCMAC和VDVs的时滞系统输出跟踪控制
针对一类不确定时滞系统,提出了一种基于TS-SCMAC和虚拟期望变量(VDV)的输出跟踪方法。整体控制输出跟踪系统具有H∞控制性能。该方法的优点是不需要系统平衡信息,简化了控制器设计。ii)总体输出跟踪系统具有H∞控制性能。此外,我们还考虑了连续搅拌槽式反应器系统的实例。数值结果验证了所提控制器的有效性。
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