A 26.5-40 GHz Stacked Power Amplifier in 130 nm SiGe BiCMOS Technology

Abstract

A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.