A programmable instruction format extension to VLIW architectures

Abstract

While very long instruction word (VLIW) architectures permit static extraction of a valuable amount of concurrency, their major drawback lies in the considerable code memory size requirements, due to the horizontal nature of the instruction set. To overcome this inefficiency, the authors propose a programmable instruction format extension, where the compiler is responsible for the choice of the best combinations of operations which are allowed to be concurrently executed. This results in a substantial saving of instruction bits, at the only expense of some additional memory for decoding circuitry. An applicative example on a sample architecture shows how performance decay is strongly limited also when the instruction width is reduced by a factor of three.<>