A Novel Scalable On-chip Switch Architecture with Quality of Service Support for Hardware Accelerated Cloud Data Centers

Abstract

This paper proposes a scalable on-chip packet switch architecture, ACCLOUD-SWITCH, for hardware accelerated cloud data centers. The proposed switch architecture adopts architectural features from high-speed computer network and network on chip (NoC) routers. ACCLOUD-SWITCH interconnects heterogeneous high-speed interfaces and is implemented on FPGA. The switch fabric runs at line speed for scalability. We propose a new work-conserving fabric arbiter that can allocate bandwidth to input/output pairs by prioritizing the switch ports and a new hybrid buffer structure for ports connected to reconfigurable regions for more efficient memory use. The switch is implemented for Xilinx Zynq SoC device to work at 40 Gbps. Our simulation results demonstrate the benefits of the proposed arbiter and the hybrid buffer structure.