Implementation of AES Using Composite Field Arithmetic for IoT Applications

Abstract

The presented work carries out a Very Large Scale Integration (VLSI) implementation of the Advanced Encryption Standard (AES) symmetric cipher to investigate for its best-suited architecture for IoT applications. Standard architectures, such as, rolling, unrolling and combinational were examined. S-box, which forms the core of AES was designed using composite field arithmetic and an optimized form was used in each architecture design to improve hardware efficiency. The design, verification and RTL synthesis of the algorithm was done using Xilinx Vivado 2018.3 simulator. Stringent area and power requirements being the prior criteria for IoT devices, the rolled architecture turned out to be the favorite candidate upon analysis of the result.