Parallel buffers for chip multiprocessors

J. Cieslewicz, K. A. Ross, Ioannis Giannakakis
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引用次数: 27

Abstract

Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among many hardware threads, implementing parallel database operators that efficiently share these resources is key to maximizing performance. A crucial aspect of this parallelism is managing concurrent, shared input and output to the parallel operators. In this paper we propose and evaluate a parallel buffer that enables intra-operator parallelism on CMPs by avoiding contention between hardware threads that need to concurrently read or write to the same buffer. The parallel buffer handles parallel input and output coordination as well as load balancing so individual operators do not need to reimplement that functionality.
芯片多处理器的并行缓冲器
芯片多处理器(cmp)为提高大型查询的数据库性能提供了新的机会。由于cmp经常在许多硬件线程之间共享执行、缓存或带宽资源,因此实现有效共享这些资源的并行数据库操作是实现性能最大化的关键。这种并行性的一个关键方面是管理并行操作符的并发、共享输入和输出。在本文中,我们提出并评估了一个并行缓冲区,该缓冲区通过避免需要并发读写同一缓冲区的硬件线程之间的争用,从而实现cmp上的操作符内并行性。并行缓冲区处理并行输入和输出协调以及负载平衡,因此单个操作符不需要重新实现该功能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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