A Calibration-Free 13b 625MS/s Tri-State Pipelined-SAR ADC with PVT-Insensitive Inverter-Based Residue Amplifier

Abstract

With the increased demand for high data throughput of next-generation wireless communication, pipelined-SAR ADC has become a popular architecture for data conversion due to its superior power efficiency. For 5G/6G wireless communication, near-GHz signal bandwidth requires the residue amplifier (RA) to settle as fast as possible with precise amplification. Previous works [1], [2], [3] have exploited open-loop RAs for high-speed data conversion. However, significant gain error and PVT-related gain variation limit its dynamic range and require gain calibration. Closed-loop RA has been proposed for accurate gain control [4], but its limited bandwidth is not suitable for high-speed applications. In [5], the comparator metastability has been explored to increase the conversion speed in a binary searching SAR topology.