{"title":"Design and implementation of a differential LNA for WiMAX system","authors":"Yu‐Lin Wang, M. Her, Chi-Feng Lin","doi":"10.1109/APCC.2009.5375602","DOIUrl":null,"url":null,"abstract":"The low noise and high gain differential Low Noise Amplifier (LNA) was designed for an IEEE 802.16 Worldwide Interoperability Microwave Access (WiMAX) application. This paper presents a 3.3 GHz to 3.8 GHz CMOS LNA with differential and cascode circuits to reduce the noise figure (NF) and enhance the gain. The LNA was fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M standard CMOS process, the cascode technique can reduce the miller effect of gate-drain capacitor C<inf>gd</inf> in order to enhance gain, and the active balun can enhance gain and reduce noise. The circuit performances were measured by using on-wafer test. The differential LNA exhibits that the noise figure is 3.3 dB ~ 3.8 dB from 3.3 GHz to 3.8 GHz, the maximum power gain S<inf>21</inf> is 14.4±0.6 dB and S<inf>31</inf> is 12.4 ± 0.5 dB. The output return loss S<inf>22</inf> and S<inf>33</inf> are less than −11 dB. The power consumption is 14.8 mW at V<inf>DD</inf>=1.2 V.","PeriodicalId":217893,"journal":{"name":"2009 15th Asia-Pacific Conference on Communications","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 15th Asia-Pacific Conference on Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCC.2009.5375602","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The low noise and high gain differential Low Noise Amplifier (LNA) was designed for an IEEE 802.16 Worldwide Interoperability Microwave Access (WiMAX) application. This paper presents a 3.3 GHz to 3.8 GHz CMOS LNA with differential and cascode circuits to reduce the noise figure (NF) and enhance the gain. The LNA was fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M standard CMOS process, the cascode technique can reduce the miller effect of gate-drain capacitor Cgd in order to enhance gain, and the active balun can enhance gain and reduce noise. The circuit performances were measured by using on-wafer test. The differential LNA exhibits that the noise figure is 3.3 dB ~ 3.8 dB from 3.3 GHz to 3.8 GHz, the maximum power gain S21 is 14.4±0.6 dB and S31 is 12.4 ± 0.5 dB. The output return loss S22 and S33 are less than −11 dB. The power consumption is 14.8 mW at VDD=1.2 V.