Hardware/Software Co-design for Evolvable Hardware by Genetic Algorithm

Abstract

A co-design architecture for the field programmable gate array (FPGA)-based evolvable hardware (EHW) system is proposed. In this architecture, a virtual reconfigurable circuit (VRC) is configured by the genetic algorithm (GA). The VRC is implemented in FPGA, and the GA is executed by a processor. The ARM processor and the NIOS II processor are used. This architecture maintains the flexibility and scalability of the VRC. This approach also has the flexibility to change the parameters or even the GA algorithm without affecting the FPGA part. Three circuits of different degrees of complexity are used to evaluate the system. Experimental results showed that the co-design was successfully implemented. In addition, compared to the NIOS II approach, the ARM approach had the advantages regarding the evolution speed and the logic utilization.