Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology

Abstract

Internet of things applications demand reusable modular designs with low-power consumption. Furthermore, many emerging applications, such as image recognition using machine learning, are low-accuracy tolerant. For these applications, the IEEE-754 half-precision arithmetic is becoming a relevant option for low-power, low-computational cost designs. This article presents a half-precision floating-point multiplier. It is implemented on 130 nm CMOS ASIC technology. The proposed multiplier IP core exhibits low-power consumption, small silicon area, and its accuracy is IEEE-754 compliant.