Power Distribution Network Capacitive Decoupling for Side-Channel Resistance

Abstract

In power side-channel attacks (SCA), the adversary observes the power leakage at the external power pin to reverse engineer the secrets embedded in sensitive circuits. Mitigation techniques are often integrated into the logic to make power consumption data independent. In this paper, we develop a new design strategy for designing the on-chip power distribution network using a decoupling capacitance to thwart the power side-channel attack. The decoupling capacitances are introduced along the power lanes in a distributed fashion, to suppress the data-leakage from the sensitive-circuit. To facilitate the computer-aided design of such PDNs, we also develop approximate heuristics to extract feature vectors from the current (I) profile of the internal logic blocks, and for feature vector propagation over the on-chip power distribution network. We study the sensitivity of decoupling capacitance value and its placement over the power distribution network. Finally, we evaluate the side-channel resistance with and without decoupling capacitance using Spice level simulations. Machine Learning (ML) classifiers are used to quantify the side-channel strength in terms of success rate for power side-channel adversary. A 100pf decoupling capacitance, in some cases, reduces the ML success rate from 80% to 21% to provide significant SCA resistance.