Energy efficient computing with tunnel FETs

Abstract

This paper reports on the state-of-the-art and recent advances concerning the tunnelling FETs as energy efficient switches, capable of operating at sub-0.5V due to their low Ioff and steep subthermal subthreshold slope (better than 60mV/decade at room temperature). Overall, it appears that the engineering of heterojunction tunnelling FETs with the application of some technology boosters similar to advanced silicon CMOS can offer the appropriate path for a high performance complementary platform for this new family of devices. More aggressive scaling of their operation voltage, below 0.1V can be achieved with new concepts like the Electron-Hole Bilayer Tunnel FET exploiting the effect of low dimensionality on the Density of States (DOS).