Analysis of BTI Induced Input Buffer Aging Based on 32nm CMOS Process

Jinmei Shi, Jiajing Cai, Henan Wu
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引用次数: 1

Abstract

This paper makes a breakthrough to accurately estimate and comprehensively analyze the transmission delay of input buffer caused by BTI aging via establishing aging model and comparing with standard logic unit. It presents the BTI aging for traditional input buffer within 10 years, designed in 32nm CMOS technology, and simulated with LTSPICE software. The use of Schmitt flip-flops as input buffers enables the circuit to increase noise tolerance and drive capability. The simulation results show that when the power supply voltage is 0.8V-1.1V, the transmission delay of input buffer will increase by 60% after 10 years under the influence of BTI aging, compared with 31% delay increment of CMOS 11-cascaded inverters under the same technology. In order to improve the reliability, the proposed technique named ICMT is introduced, which contributes to reducing 34% propagation delay for the input buffer.
基于32nm CMOS工艺的BTI诱导输入缓冲器老化分析
本文通过建立老化模型并与标准逻辑单元进行比较,突破了准确估计和全面分析BTI老化引起的输入缓冲器传输延迟的问题。采用32nm CMOS工艺设计了传统输入缓冲器的BTI老化,并利用LTSPICE软件进行了仿真。使用施密特触发器作为输入缓冲器可以提高电路的噪声容忍度和驱动能力。仿真结果表明,当电源电压为0.8V-1.1V时,受BTI老化影响,10年后输入缓冲器的传输延迟将增加60%,而相同技术下CMOS 11级联逆变器的延迟增量为31%。为了提高系统的可靠性,本文引入了ICMT技术,使输入缓冲区的传输延迟降低了34%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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