{"title":"Built-in test strategies for military systems","authors":"D.H. Merlino, J. Hadjilogiou","doi":"10.1109/ARMS.1989.49575","DOIUrl":null,"url":null,"abstract":"Using the reliability models from MIL-STD-217E, a builtin test strategy (BIT) is developed. This approach illustrates that the BIT implementation is affected by temperature, environment, part quality level, electronic circuitry and packaging. All of these factors must first be considered as to their effects on the expected failure before embarking on a given BIT design approach. Most notably, failure rate distributions between the device electronics and package pins/interconnects are used in the approach discussed. The analysis compares the expected failure distributions for a typical line replaceable module (LRM) in both a ground benign (Gb) and an aircraft uninhibited fighter (Auf) environment to illustrate the resulting different BIT implementation.<<ETX>>","PeriodicalId":430861,"journal":{"name":"Proceedings., Annual Reliability and Maintainability Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Annual Reliability and Maintainability Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARMS.1989.49575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Using the reliability models from MIL-STD-217E, a builtin test strategy (BIT) is developed. This approach illustrates that the BIT implementation is affected by temperature, environment, part quality level, electronic circuitry and packaging. All of these factors must first be considered as to their effects on the expected failure before embarking on a given BIT design approach. Most notably, failure rate distributions between the device electronics and package pins/interconnects are used in the approach discussed. The analysis compares the expected failure distributions for a typical line replaceable module (LRM) in both a ground benign (Gb) and an aircraft uninhibited fighter (Auf) environment to illustrate the resulting different BIT implementation.<>