{"title":"Design and implementation of modulator ASIC for CDMA WLL system","authors":"J. Lee, Y. Jeong, K. Ha","doi":"10.1109/ICPWC.1997.655546","DOIUrl":null,"url":null,"abstract":"We present the design and implementation of modulator ASIC in a direct sequence code division multiple access (DS-CDMA) wireless local loop (WLL) system. The WLL system consists of two links: one is a forward link (fixed station-mobile); the other is a reverse link (mobile-fixed station). We only consider the issues of the ASIC design and implementation in the forward link. We present an efficient structure of the forward link in the WLL system. According to the proposed structure, the modulator ASIC is composed of two channels which perform channel coding, block interleaving and spreading, and with four baseband filters. The ASIC is fabricated using a 0.6 /spl mu/m CMOS process with 40 k gates and was successfully tested on a WLL test-bed system.","PeriodicalId":166667,"journal":{"name":"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPWC.1997.655546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present the design and implementation of modulator ASIC in a direct sequence code division multiple access (DS-CDMA) wireless local loop (WLL) system. The WLL system consists of two links: one is a forward link (fixed station-mobile); the other is a reverse link (mobile-fixed station). We only consider the issues of the ASIC design and implementation in the forward link. We present an efficient structure of the forward link in the WLL system. According to the proposed structure, the modulator ASIC is composed of two channels which perform channel coding, block interleaving and spreading, and with four baseband filters. The ASIC is fabricated using a 0.6 /spl mu/m CMOS process with 40 k gates and was successfully tested on a WLL test-bed system.