Design and Analysis of Low Power CMOS SRAM Cells 7T and 9T

Abstract

7T and 9T SRAM cells are compared by the software Cadence Virtuoso tool using 180nm technology. Designing a memory of low power consumption is a challenging concept in the present time. The average power consumption of 7T and 9T SRAM cells is compared. The main parameter of SRAM Static Noise Margin (SNM) is evaluated and properly discussed. The results show that the Write delay of 9T has the minimum delay as compared to 7T. The paper makes an attempt to perceive a more efficient and stable SRAM memory. The market demand is to pack more and more devices in a single circuit or a chip. A vision is provided to ensure that the chip does not contain any apparent fabrication defects.