Digital implementation of diode-clamped three-phase three-level SVPWM inverter

Abstract

The conventional modulation strategies for diode-clamped three-phase three-level inverter have some disadvantages, such as switching loss of switching device. This paper presents a novel space vector pulse width modulation (SVPWM) scheme to reduce switching loss. Using this novel modulation strategy, the changing of switch states cause only one single phase voltage change every time. In this way, the inverter generates similar output voltage as that under the common strategies, whereas the switching loss is reduced. The proposed scheme has been digitally implemented by using TMS320F240 and its feasibility has been verified by the experimental results.