Interleaver design for spectrally-efficient bit-interleaved LDPC-coded modulation

Abstract

A design methodology for interleavers in bit-interleaved coded modulation systems deploying (binary irregular) low-density parity-check (LDPC) codes and higher-order modulation is presented. The interleaver is introduced to balance unequal error protection characteristics inherent in coding and modulation. For this purpose, mapping distributions are used to describe the interleaver configuration. Furthermore, an optimization procedure is applied to derive good mapping distributions for practical block lengths in the order of 102-103 bits. Exemplary numerical results are presented for higher-order modulation and LDPC codes as defined in the IEEE standard 802.11n.