Efficient parallel finite field modular multiplier

Abstract

In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)/sup 2/ 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is T/sub AND/ + [log/sub 2/(m + 1)]T/sub XOR/. The proposed architectures are highly modular and well suited for high speed VLSI implementations.