Design of IC implementation of 16/spl times/16 CNN with serial-parallel input

Abstract

This paper presents the design of a digital integrated circuit implementation of fully programmable cellular neural network for binary images processing. It consists of 16/spl times/16 cells and the memory able to store the image. The circuit is design in the standard cell style CMOS 0.35 /spl mu/m technology. The advantages of the digital CNN are: high reliability and robustness to the manufacturing parameters disturbances in comparison with analogue implementation. The disadvantages of this approach are: higher power consumption and larger IC silicon area. The paper presents the architecture of the network, as well as its components, the estimated system parameters (calculation speed, power consumption and density of cells) in comparison to selected CNN designs.