Hardware Acceleration for Finite Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations with Field Programmable Gate Arrays

Abstract

Custom hardware acceleration of electromagnetics computations leverages favorable industry trends, which indicate reconfigurable hardware devices such as field programmable gate arrays (FPGAs) may soon outperform general purpose CPUs. We present a new striping method for efficient sparse matrix-vector multiplication implemented in a deeply pipelined FPGA design. The effectiveness of the new method is illustrated for a representative set of finite element matrices