A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline

Abstract

We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed 512-kb DP SRAM macro is designed using 28-nm HKMG technology, from which we successfully observed 1-GHz operation at 1.0 V, 190 mV Vmin improvement, and 21% power reduction compared to a conventional assist.