Algorithmic Aspects of VLSI Layout

Abstract

Issues in timing driven layout, M. Marek-Sadowska binary formulations for placement and routing problems, M. Sriram, S.M. Kang a survey of parallel algorithms for placement, P. Banerjee near optimal fast solution to graph and hypergraph partitioning, F. Makedon, S. Tragoudas LP formulation of global routing and placement, T. Lengauer, M. Lugering circuit partitioning algorithms based on geometry model, T. Asano & Tokuyama on the Manhattan and knock-knee routing modes, D. Zhou, F.P. Preparata a note on the complexity of Stockmeyer's floorplan optimization technique, T.C. Wang, D.F. Wong the virtual height of a straight line embedding of a plane graph, T. Takahashi, Y. Kajitani routing around two rectangles to minimize the layout area, T. Gonzalez, S.L. Lee.