Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology

Abstract

This paper presents a new technique to compensate the comparator delay dispersion caused by variable input overdrive. The technique is composed of three main blocks, namely, conventional comparator, fixed delay block and variable delay block. The variable delay block is controlled such that it implements the inverse overdrive-delay characteristics of the conventional comparator. Therefore, the overall delay dispersion of the technique is effectively reduced. The technique is implemented in 65nm technology. The measurement and simulation results show that the delay dispersion of the proposed technique is 10% of its counterpart in the conventional comparator. The active area of the technique 267.8μm2 and the measured power consumption is 273μW at 200MHz.