H. Ishihara, M. Miyama, Y. Matsuda, Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto
{"title":"A VGA 30-fps optical-flow processor core based on Pyramidal Lucas and Kanade algorithm","authors":"H. Ishihara, M. Miyama, Y. Matsuda, Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ASSCC.2007.4425762","DOIUrl":null,"url":null,"abstract":"This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 times 3.00 mm2 and 600 mW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 times 3.00 mm2 and 600 mW.