Early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system

Martim Rosado, S. Mallios, P. Tomás, N. Roma, A. David
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Abstract

The Compact Muon Solenoid (CMS) high-granularity calorimeter (HGCAL) upgrade for CERN's Large Hadron Collider (LHC) high-luminosity phase is a detector with more than 6 million channels that will provide precise sensing and measurement of position, timing, and energy of the particles produced in the collisions of the beams. The HGCAL electronics are a large and complex set of processing systems split into front-end and back-end. The front-end, located in the experimental cavern, consists of $\boldsymbol{\approx 150}$ thousand radiation tolerant ASICs. The high-density FPGA-based back-end is housed away from the radiation area in a set of Advanced Telecommunications Computing Architecture (ATCA) boards and crates hosting $\boldsymbol{\approx 100}$ FPGAs. Each ATCA back-end board will comprise one (or two) FPGAs, managing up to $\boldsymbol{\approx 120}$ optical links, each providing a transmission rate of 10.24 Gb/s between the back-end and the front-end electronics. Each back-end FPGA is responsible for configuring and monitoring up to $\boldsymbol{\approx 3500}$ front-end ASICs and will be controlled by software running on a back-end MPSoC that provides the entry point for the whole control procedure. This paper presents the design and implementation of the prototyping infrastructure deployed to test and validate the slow-control block of the HGCAL back-end electronics, together with the related interfaces with the controller MPSoC and the front-end transceiver ASICs. The required functionalities have been validated with a ZCU102 Xilinx Ultrascale+ development board, which emulated the back-end elements that are still under development and not yet available for this comprehensive test. This development board was connected to other custom ASIC development boards via optical links, emulating the front-end side of the system, also still under development. Besides providing reliable testing and validation of the operation of the whole infrastructure, the prototyping platform also allowed to attain the required software/hardware portability that ensures easy integration/replacement of all the (still) emulated components with their final implementations.
CERN大型强子对撞机CMS高粒度量热计慢控系统的早期原型设计与测试
CERN大型强子对撞机(LHC)高亮度相位的紧凑型μ子螺杆管(CMS)高粒度量热计(HGCAL)升级是一个拥有超过600万个通道的探测器,将提供精确的传感和测量光束碰撞中产生的粒子的位置、时间和能量。HGCAL电子系统是一套庞大而复杂的处理系统,分为前端和后端。前端位于实验洞穴中,由$ $ boldsymbol{\ \ 150}$ $ 1000耐辐射asic组成。高密度基于fpga的后端被安置在一组高级电信计算架构(ATCA)板和板条箱中,远离辐射区域,托管$ $ boldsymbol{\ \约100}$ fpga。每个ATCA后端板将包括一个(或两个)fpga,管理最多$ $ boldsymbol{\ \约120}$光链路,每个在后端和前端电子设备之间提供10.24 Gb/s的传输速率。每个后端FPGA负责配置和监控最多$ $前端asic,并将由在后端MPSoC上运行的软件控制,该软件为整个控制过程提供入口点。本文介绍了用于测试和验证HGCAL后端电子器件慢速控制块的原型基础设施的设计和实现,以及与控制器MPSoC和前端收发器asic的相关接口。所需的功能已经通过ZCU102 Xilinx Ultrascale+开发板进行了验证,该开发板模拟了仍在开发中的后端元素,尚未用于本次全面测试。该开发板通过光链路连接到其他定制的ASIC开发板,模拟系统的前端,也仍在开发中。除了提供整个基础架构运行的可靠测试和验证外,原型平台还允许实现所需的软件/硬件可移植性,从而确保所有(仍然)仿真组件与其最终实现的轻松集成/替换。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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