A Compact Model for Reliability Simulation of Deep-Submicron MOS Devices and Circuits

Zhi-Yuan Cui, J. Liou
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Abstract

Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and measured data obtained from devices fabricated from the 0.18-μm CMOS technology have been included in support of the model development.
深亚微米MOS器件和电路可靠性仿真的紧凑模型
CMOS技术的持续缩小导致对Spice-like可靠性模型的需求日益迫切,该模型能够预测MOS器件和ic的长期退化。在本文中,我们基于行业标准BSIM3模型和mosfet阈值电压和迁移率的经验退化表达式开发了这样一个模型。该模型通过Verilog-A在Cadence Spectre中实现,并且从采用0.18 μm CMOS技术制造的器件中获得的测量数据已包括在内,以支持模型的开发。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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