Design and implementation of 16 tap FIR filter for DSP Applications

Abstract

In this paper, two novel methods to design a high speed, low power 16-Tap 32-bit digital FIR filter for DSP application are proposed. The basic building blocks of the FIR filters are adders, multipliers and delay elements. In the proposed work, proposed filter-1 is designed using carry increment adder and 32-bit Vedic multiplier and proposed filter2 is designed using altered carry skip adder and 32-bit Vedic multiplier. FIR filter architectures with 16-TAP is developed using Verilog HDL and implemented using $45 \eta \mathrm {m}$ technology. The ASIC result shows the proposed-1 and proposed-2 16-TAP 32-bit filter has power dissipation of 7.36mW and 7.282mW with the delay of $6.79 \eta \mathrm {S}$ and $7.23 \eta \mathrm {S}$ respectively.