Analysis of low power reduction in voltage level shifter

Abstract

The preserver for portable devices is satisfied by developing CMOS technology. Voltage level shifter is introduced here using adaptive voltage level technique progression of curtailing the power dissipation and power consumption. Power dissipation is the most important parameter here, the adaptive voltage level technique is apply in present work mitigate the power dissipation. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology which is increase the ground potential and AVLS (adaptive voltage level supply) which is raise supply potential. The purpose of the design to investigate the static power and power dissipation for low voltage level shifter for proposed design style. This design is valuable in designing the system that consumes less power. The simulation and performance analysis of proposed circuit evaluate in cadence virtuoso tool. The AVL technique based voltage level shifter compared to conventional design that based on power consumption and power dissipation.