Direct digital frequency synthesizer with designable stepsize

Abstract

The Variable Resolution (VR) technique for direct digital frequency synthesis (DDFS) is introduced. By manipulating the number of phase states available to the DDFS accumulator, it is shown that the frequency resolution can be designed to desired values while keeping binary arithmetic circuit structures. Examples focus on realizing exact decimal resolution and prime rational fractions thereof, such as 1/3. Measurements not only validate this design approach, but also show worst case output spurious signal magnitudes below −73 dBc from initial implementations