Fault-tolerance and reconfigurability issues in massively parallel architectures

Abstract

Fault tolerance is a basic requirement for many applications of massively parallel architectures; these, in turn, provide the opportunity to exploit regularity of the architecture to perform reconfiguration with a relatively simple interconnection structure and reduced number of spare elements. Interconnection complexity is taken as the guiding figure of merit. Reconfiguration approaches based on a stringent channel width limitation are presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing the presence of faults in bus segments and switches as well as in PEs.