Low Phase-Noise Multi-phase Oscillators Based on Differential Self-Timed Rings

Jiawei Feng, Mei Jiang, Wei Song, Peng Zhao
{"title":"Low Phase-Noise Multi-phase Oscillators Based on Differential Self-Timed Rings","authors":"Jiawei Feng, Mei Jiang, Wei Song, Peng Zhao","doi":"10.1109/ICCS52645.2021.9697260","DOIUrl":null,"url":null,"abstract":"A low phase-noise multi-phase oscillators based on differential self-timed rings (DSTRO) is presented. Due to the improved differential Muller C-element, a higher oscillation frequency and 3dB phase noise reduction can be achieved when compared to conventional self-timed-rings oscillator (STRO) with the same number of stages, simultaneously obtaining more accurate resolution and doubled phase number. The circuits have been designed and simulated employing 65nm CMOS technology. It achieves −91.29 dBc/Hz PN@1MHz and −117.26 dBc/Hz FoM@1MHz with the power consumption of 2.35 mW at a 1.2V power supply. The results show that robustness and power efficiency are improved.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS52645.2021.9697260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A low phase-noise multi-phase oscillators based on differential self-timed rings (DSTRO) is presented. Due to the improved differential Muller C-element, a higher oscillation frequency and 3dB phase noise reduction can be achieved when compared to conventional self-timed-rings oscillator (STRO) with the same number of stages, simultaneously obtaining more accurate resolution and doubled phase number. The circuits have been designed and simulated employing 65nm CMOS technology. It achieves −91.29 dBc/Hz PN@1MHz and −117.26 dBc/Hz FoM@1MHz with the power consumption of 2.35 mW at a 1.2V power supply. The results show that robustness and power efficiency are improved.
基于差分自定时环的低相位噪声多相振荡器
提出了一种基于差分自定时环(DSTRO)的低相位噪声多相振荡器。由于改进的差分穆勒c -单元,与相同级数的传统自定时环振荡器(STRO)相比,可以实现更高的振荡频率和3dB的相位降噪,同时获得更精确的分辨率和两倍的相位数。采用65nm CMOS技术对电路进行了设计和仿真。在1.2V电源下,功耗为2.35 mW,可实现−91.29 dBc/Hz PN@1MHz和−117.26 dBc/Hz FoM@1MHz。结果表明,该方法提高了鲁棒性和功耗效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信