{"title":"Low Phase-Noise Multi-phase Oscillators Based on Differential Self-Timed Rings","authors":"Jiawei Feng, Mei Jiang, Wei Song, Peng Zhao","doi":"10.1109/ICCS52645.2021.9697260","DOIUrl":null,"url":null,"abstract":"A low phase-noise multi-phase oscillators based on differential self-timed rings (DSTRO) is presented. Due to the improved differential Muller C-element, a higher oscillation frequency and 3dB phase noise reduction can be achieved when compared to conventional self-timed-rings oscillator (STRO) with the same number of stages, simultaneously obtaining more accurate resolution and doubled phase number. The circuits have been designed and simulated employing 65nm CMOS technology. It achieves −91.29 dBc/Hz PN@1MHz and −117.26 dBc/Hz FoM@1MHz with the power consumption of 2.35 mW at a 1.2V power supply. The results show that robustness and power efficiency are improved.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS52645.2021.9697260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A low phase-noise multi-phase oscillators based on differential self-timed rings (DSTRO) is presented. Due to the improved differential Muller C-element, a higher oscillation frequency and 3dB phase noise reduction can be achieved when compared to conventional self-timed-rings oscillator (STRO) with the same number of stages, simultaneously obtaining more accurate resolution and doubled phase number. The circuits have been designed and simulated employing 65nm CMOS technology. It achieves −91.29 dBc/Hz PN@1MHz and −117.26 dBc/Hz FoM@1MHz with the power consumption of 2.35 mW at a 1.2V power supply. The results show that robustness and power efficiency are improved.