Stability and Reliability Performance of Double Gate Junctionless Transistor (DG-JLT) 6T SRAM

Abstract

This work presents the impact of interface trap charges present at $\mathbf{Si}/\mathbf{SiO}_{2}$ interface on $\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$ ratio of double gate junctionless transistor (DG-JLT). DG-JLT is used to implement $6T$ SRAM and its various stability performance metrics are studied including Hold static noise margin (HSNM), Read static noise margin (RSNM), Static voltage noise margin (SVNM) and Static current noise margin (SINM). Reliability of SRAM is also studied by analyzing stability parameters in the presence of interface trap charges. As trap charges originate due to different type of damages like hot carrier degradation, stress etc., therefore two density profile of interface trap charges, uniform and step function profile are considered. Shift in $\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$ ratio of the device and various stability parameters is observed in the presence of interface trap charges. The amount of shift noted is more in uniform profile compared to step function profile as traps are present only in half portion of the device in case of step function profile. In this work SILVACO 3-D ATLAS device simulator has been used for simulation.