Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Abstract

Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.