A Dynamic Scan Chain Reordering for Low-Power VLSI Testing

Chul-ki Baek, In-Sub Kim, Jung-Tae Kim, Yong-Hyun Kim, Hyoung B. Min, Jae-Hoon Lee
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引用次数: 5

Abstract

Low-power electronic circuit design for VLSI (Very Large Scale Integrated) testing is one of key design issues since power consumption is increased dramatically during test operations due to heavy transitions. Scan chain reordering has been one of the efficient low-power test technology to solve this problem. In this paper, we propose a new dynamic scan cell reordering technique that improves power reduction ratios of the traditional static reordering of scan cells. This technique is simple to implement, and can be easily applied to several scan chain based test circuits. Experimental results show that the proposed method can reduce power by up to 23% and 15% of the maximum and average power consumption for ITC99 benchmark circuits.
低功耗VLSI测试的动态扫描链重排序
VLSI(超大规模集成电路)测试的低功耗电子电路设计是关键设计问题之一,因为在测试操作期间,由于大量的转换,功耗急剧增加。扫描链重排序是解决这一问题的一种有效的低功耗测试技术。本文提出了一种新的动态扫描单元重排序技术,提高了传统静态扫描单元重排序的功耗降低率。该技术易于实现,可以很容易地应用于几种基于扫描链的测试电路。实验结果表明,该方法可将ITC99基准电路的最大功耗和平均功耗分别降低23%和15%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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