Negative Bias Temperature Instability Benefits on Power Reduction Techniques

Abstract

This article stabilizes the significant link between static power and reliability. More particularly, shows the general leakage reduction techniques provide a valid solution to reduce leakage current under Negative Bias Temperature Instability (NBTI) condition. The state preserving leakage reduction techniques reduces the leakage power effectively, while the NBTI on PMOS transistor increases the threshold voltage which leads to the further leakage and total power reduction. This work investigates the effect of NBTI on leakage power reduction techniques. Three state preserving power reduction techniques namely Forced Stacking, Sleepy Stack and Feedback Sleeper-Stack circuit techniques have been applied to C17 logic circuit to show that leakage power, total power, and power-delay products take benefits from NBTI-induced aging. The result shows that Feedback Sleeper-Stack techniques with NBTI achieve 90% leakage reduction, 64.6% total power reduction, 50.8% performance improvement with a delay penalty of 28% over the base case in 2 year under iso-area condition.