Design and Analysis of 16-bit Vedic Multiplier using RCA and CSLA

Abstract

In this paper we have designed and analysed vedic multiplier using RCA and CSLA.The multiplier is a crucial part of digital signal processors. High-speed multiplier hardware is in extremely high demand. Speed, power, and area are three of the most important variables in determining how successful a multiplier is. The proposed Vedic multiplier utilizes the CSLA to increase the speed and efficiency of the multiplication process. The Urdhva-Tiryakbhyam algorithm is applied to break down the input operands into smaller sub-blocks, and the intermediate products are obtained by multiplying the sub-blocks using the algorithm. The final product is then obtained by adding the intermediate products using the CSLA. However, the CSLA is not an area-efficient one due to the dual RCA design.Using the CSLA,RCA,Halfadders,fulladder in Verilog HDL, a 16-bit Vedic multiplier is created using Modelsim to simulates and synthesised using Xilinx ISE 14.7. In this project we have implemented Vedic Multiplier using CSLA and compared it with the Vedic multiplier using RCA.The synthesis result is showns that CSLA has 3% greater area than RCA. CSLA has Reduced delay by 12%than Vedic ultiplier using RCA.