Benchmarking Different MapReduce Implementations for Computer-Aided Hardware Development

Abstract

In the design of fast arithmetic circuits, the two's complement number representation can be alternatively replaced by a signed digit number representation. Compared to standard full adders used in two's complement arithmetic, signed digit adder cells offer the potential for improved performance. Designing an efficient signed digit adder cell leads to the problem of analyzing 2 to the power of 44 truth tables originating from different signed digit encodings. Since different digit encodings can produce identical truth tables, it is favorable to reduce this large number of truth tables by identifying identical ones. We introduce a novel approach for the solution of this problem using the MapReduce programming model. We take a step towards solving this problem using three different implementations of MapReduce (Hadoop, Disco, and MR-MPI) and compare their performance on an Opteron-based cluster using up to 64 physical cores.