14nm FinFET based 0.8V Supply 25Gbps Subsampler and Phase Detector Circuits for All Digital CDR

Abstract

In this paper, the design of subsampler and phase detector circuits at 14nm technology node (FinFET) is presented. The design is carried out on cadence virtuoso with a supply voltage of 0.8V and across process corners (ss, sf, tt, fs, ff). The designed subsampler and phase detector circuits are in compliance with the All-digital clock and data recovery (ADCDR) circuit and which is applicable to passive optical networks of 4 channels with a speed of 25Gbps per channel by consuming a power dissipation of 0.9728 mW.