A Self-Timed Ring based TRNG with Feedback Structure for FPGA Implementation

Abstract

This paper describes a hardware design of self-timed ring based true random number generator (TRNG) that is suitable for information security applications. To reduce the hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which reduces the number of ring stages. A set of statistical tests for randomness defined by NIST SP 800–22 were performed by extracting 20 million bits of binary sequences generated by our FSTR-TRNG, and it was found that all 15 tests were satisfied the criteria. The FSTR-TRNG occupies 46 slices of Spartan-6 FPGA device and approximately 2,500 gate equivalents (GEs) with a 180 nm CMOS standard cell library.