Design of low power 4-bit Flash ADC in 90nm CMOS Process

Abstract

In this paper design of low power 4-bit Flash ADC for high frequency applications is presented. The power consumption of the Flash ADC in this work has been reduced in two phase. In the first phase a low power dynamic comparator has been designed which consumes 329.332 µW power. In the second phase a low power Fat tree encoder has been designed. The proposed encoder design uses reduced number of gates than the conventional design. As a result the average power dissipation of the encoder block is 43.6µw. The above mentioned Flash ADC is designed using CMOS 90nm Technology in Cadence tool. The proposed design has a power consumption of 5.1096 mW at IV power supply and at a sampling frequency of 1GHz.