Microarchitecture of HaL's CPU

Abstract

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.