A 5-Bit Building Block for 20 MHz NMOS A/D Converters

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468812

H. Fiedler, B. Hoefflinger, W. Demmer, P. Draheim

引用次数: 3

Abstract

This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.

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用于20mhz NMOS A/D转换器的5位构建块

本文提出了一种单片全并行5位NMOS a /D转换器。该芯片采用最小特征为7 μm的标准金属栅增强/耗尽技术制造。它包含31个频闪比较器、锁存器、组合逻辑、一个5 × 31 ROM、TTL缓冲器和一个4位DAC。这使它成为两步8位转换器的构建块。该芯片以每秒20兆样本的速度被完全表征。当步长为80 mV时，直流线性度优于1/4 LSB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

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