Modeling of CGRA to Improve Power Efficiency for Computationally Intensive Application

Abstract

To achieve high computational efficiency by maintaining low power and area requirement is becoming vitally important task for many computationally intensive applications in mobile devices. Designing an architecture for such complex application on ASIC is the traditional method which gives good performance by sacrificing flexibility. The many researchers are trying to achieve both performance and flexibility by exploring CGRA architecture which is a alternative of FPGA. This paper present a coarse grained architecture model for implementing low power complex application.