Adjustable low consumption circuit for monitorization of power source voltages in a SoC

Rodrigo Duarte, J. Paisana, Marcelino B. Santos, Floriberto A. Lima
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Abstract

This paper proposes an architecture for a power good comparator (PGC) designed to be used in the monitorization of supply voltages of a system-on-chip (SoC). The architecture includes a string of resistors, a comparator, a programmable debouncer and two multiplexers. This architecture was design for very low power consumption and to monitor 4 VDDs. I was implemented using TSMC 65 nm CMOS technology for VDD values of 0.9, 1.2, 1.8 and 3.3 V, with 8 programmable levels of debouncing from 3.2 mus to 32.4 mus. The PGC maximum consumption is 3.54 muA. The output signal presents a digitally adjustable hysteresis curve, with a high threshold voltage of 93% and a low threshold voltage of 90% of VDD. Practical implementation details are presented, namely the requirement for level-converters and for a bulk bias selector in the input multiplexer.
用于监控SoC电源电压的可调低功耗电路
本文提出了一种用于片上系统(SoC)电源电压监测的功率良好比较器(PGC)体系结构。该体系结构包括一串电阻、一个比较器、一个可编程除杂器和两个多路复用器。该体系结构是为非常低的功耗和监控4个vdd而设计的。I采用台积电65nm CMOS技术实现,VDD值为0.9,1.2,1.8和3.3 V,具有8个可编程电平,从3.2 μ s到32.4 μ s。PGC最大功耗为3.54 muA。输出信号呈现数字可调迟滞曲线,高阈值电压为93%,低阈值电压为VDD的90%。给出了具体的实现细节,即对电平转换器和输入多路复用器中批量偏置选择器的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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