Low power, high speed PLL fabricated in UTSi/sup (R)/ process

2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280) Pub Date : 2002-06-03 DOI:10.1109/RFIC.2002.1011947

G. Wu, D. Kelly, D. Staab, P. Denny

引用次数: 1

Abstract

A CMOS phase locked loop (PLL) design achieves GHz performance, low phase noise, low spurious side-bands and extremely low power (1V, 1GHz, and <1mA of current.) The design is fabricated in 0.5/spl mu/m UTSi/sup (R)/ SOI process which has been previously described [Reedy, 1999].

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低功耗，高速锁相环制造的UTSi/sup (R)/工艺

CMOS锁相环(PLL)设计可实现GHz性能、低相位噪声、低杂散边带和极低功耗(1V、1GHz和<1mA电流)。该设计是在0.5/spl mu/m UTSi/sup (R)/ SOI工艺中制造的，该工艺之前已经描述过[Reedy, 1999]。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280)

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