FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area

Abstract

In FinFET SRAM, width quantization and variation in silicon thickness are major challenges impacting stability and manufacturability. We propose a methodology to improve the stability of an SRAM cell by co-optimizing the different transistor fin combinations (relative sizing of different transistors) and silicon fin thickness (of FinFET) at iso-area. At iso-area, read SNM can be increased approx. 2X by varying fin-combination while decreasing write margin by 17%. Further, at iso-area and stability, we propose that silicon fin thickness constraint can be relaxed in FinFETs to improve the manufacturability and reduce process variability. Increasing the silicon fin thickness by approx. 50%, degrades read SNM by 10% while negligibly affecting write margin and increasing access time by 36%. Increased silicon thickness reduces body thickness variation in FinFETs, resulting in reduced device mismatch among transistors in an SRAM cell.