Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier

Abstract

We propose two approximate leading one detector (LOD) designs and an approximate adder (for summing two logarithms) that can be used to improve the hardware efficiency of the Mitchell logarithmic multiplier. The first LOD design uses a single fixed value to approximate the ‘d’ least significant bits (LSBs). For d=16 this design reduces the hardware cost by 19.91% compared to the conventional 32-bit Mitchell multiplier and by 15.19% when compared to a recent design in the literature. Our design is smaller by 32.33% and more energy-efficient by 56.77% with respect to a conventional Mitchell design. The second design partitions the ‘d’ bits into smaller fields and increases the accuracy by using a multiplexing scheme that selects a closer approximation to the actual input value. This design reduces the hardware cost by 17.98% compared to the original Mitchell multiplier and by 13.15% when compared to the other recent design. Our design is smaller by 29.17% and more energy-efficient by 56.18% with respect to the conventional Mitchell design. In the approximate adder, the ‘m’ least significant bits are set to a fixed bias of alternating ones and zeros. The optimal values of ‘d’ and ‘m’ are chosen to preserve the full accuracy of the conventional Mitchell multiplier while reducing the hardware cost. The new designs produce increased signed errors for inputs less than or equal to 216 but for larger numbers the accuracy is equal to that of the conventional Mitchell multiplier. The approximation affects only the $2^{16} -1$ smallest input values out of $2^{32} -1$. The new approximate multipliers are suitable for applications where approximation errors affecting the least significant digits can be tolerated.